Differential Power Analysis Countermeasure for Improved DES with Dynamic Key Management

  • Toseef Abid
  • Muhammad ali


Leakage of information in the form of side channel, from cryptographic hardware has opened up new ideas for intruders to break their security. This leakage is present in all type of hardware whether cards, FPGAs or ASICs smart. One of the most popular and effective information leakage is power. Differential Power Attacks (DPA) due to their effectiveness has become a great threat in the field of cryptography. In this paper, a countermeasure based on random power masking to avoid DPA is proposed for FPGA based hardware implementation of a dynamic key management for Improved Data Encryption Standard (IDES). Dynamic key management include three different key reconfiguration systems which can independently be used to generate sub-keys. Hardware implementation include, a 16 staged fully pipelined IDES with conventional Data Encryption Standard (DES) based, Linear Feedback Shift Register (LFSR) based, and Chaos Logistic Register (CLR) based key scheduling system. IDES having a 96 bit architecture which is more complex making it more immune to cryptographic analysis can give more throughput in as compared to simple DES. Three different key scheduling systems having 128 bit architecture includes more security in comparison to the 64 bit key systems. Implementation results of Virtex 7 series FPGA are operation frequency of 570 MHz and a throughput of 54.72 Gb/s.