Implementation of VANETs Using FPGA-based Hardware Test-Bed Approach for Intelligent Transportation System
Vehicular Ad-hoc Network (VANET) is a very active and demanding research field in recent days that plays a vital role in road safety applications. This develops a communication network between vehicles travelling on roads for inter-vehicular direct communication within their radio range. Respective road-side units (RSUs) also needs to be installed for indirect communication between vehicles which are out of radio range of each other. This paper presents VANET with its classifications and the protocol that is being used in detail. The simulation scenarios describe behavioral models for each classification and propose a hardware test-bed approach by simply incorporating respective verilog codes on any FPGA chip as per hardware requirement. This develops a small and simple kit at very basic level to connect our required sensors, burn the coding on FPGA and get the response as verification before going for real-time implementation in road traffic environment. This makes this safety critical application even safer. The futuristic approach opens the door for researchers to go with hardware approach for real-time traffic environments with this added advantage of hardware re-configurability that can be implemented accordingly.