Algorithm for Hardware Torjan Avoidance in Network-on-chip

  • Naveed Khan Baloch


Network on Chip (NoC) is the promising solution to the existing scalability issues in System on Chip (SoC). However, it is exposed to security threats like extraction of secret information from IP cores, availability of network or information on time which is called Hardware Trojan. In this paper, we propose an efficient hardware trojan detection and avoidance technique. Trojans can be inserted at various locations in the network i.e. links and internal modules of the router. These trojans affect the performance of the chip. We have selected trojans that are inserted in the internal modules and results in increased latency and permanent deadlock situations. The proposed Trojan detection and avoidance algorithm named as Bypassing Trojan Affected Router (BTER) is capable of avoiding a trojan effected router in a 2D mesh NoC architecture by modifying the routing algorithm. We use four traffic patterns uniform, shuffle, transpose and tornado for performance evaluation. Results show that proposed technique not only provide better reliability but also decreases latency at least 2 times in case of the uniform traffic pattern, 1.5 times in case of shuffle pattern and transpose pattern 1.2 times in case tornado as compared to the state of the art techniques.